In static random access memories (SRAMs), there is a specification known as "write high to data don't care" (TWHDX) which must be zero. The "write high" refers to a write enable signal (*WE) switching from a logic low to a logic high. The asterisk (*) is used to indicate that the signal is active at a logic low. When the write enable signal *WE is a logic low, the SRAM is in a write mode. When signal *WE is a logic high, the SRAM is in a read mode. Consequently, the TWHDX specification relates to the time that the data must be valid with respect to the SRAM changing from the write mode to the read mode. In particular, the requirement is that the data on the input can change simultaneously with a change from the write mode to the read mode without the new data, which is considered invalid, being written into the SRAM. This is a reasonable expectation of a user of the SRAM that data on the input will not be written if write enable signal *WE is switched to a logic high. In practice this specification is more difficult to achieve than would be immediately apparent.
The problem is that the invalid data may reach the memory cell before the write enable signal can turn off the write circuitry. There are data lines which are written onto in the write mode and which are sensed in the read mode. Memory cells are arrayed at intersections of word lines and bit line pairs. The word lines are selectively enabled by a row decoder. The bit line pairs are selectively coupled to the data lines via a column decoder. A memory cell is selected when its word line is enabled and its bit line pair is coupled to the data lines. In switching from the write mode to the read mode, the write circuitry is decoupled from the data lines in response to the write enable signal switching from a logic low to a logic high. There is a write enable buffer which causes a delay in the write enable signal being able to effectively decouple the write circuitry from the data lines. If the invalid data reaches the data lines then there is a risk that the selected memory cell will be written into with the invalid data. There is then a race condition between the write enable buffer and the write circuitry. The solution has been to add delay in the write circuitry to ensure that the buffered write enable signal reaches the write circuitry before the write circuitry outputs the invalid data onto the data lines. Adding delay in order to meet the requirement that TWHDX be zero adds to the time required to perform a write. Consequently, the TWHDX requirement adversely affects other write specifications.
Not only must the TWHDX specification be met but it is desirable that it be exceeded for guard banding purposes. Although guard banding is generally considered most desirable from a manufacturing standpoint for reasons such as testing, in this case guard banding is also desirable for the user. It is desirable that the SRAM actually ignore data changes that occur a few nanoseconds before the write to read switch because the user may have difficulty ensuring that the data doesn't change before signal *WE changes. These difficulties may arise from his own timing circuitry as well as printed circuit board layout problems. Consequently, it is desirable that the actual TWHDX of the SRAM be negative by a small amount, such as two nanoseconds (ns) using current MOS technology. Ensuring that the TWHDX specification is met has resulted in a speed penalty in writing.